1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly to methods of integrating non-planar transistors with variable channel widths into a bulk semiconductor CMOS process.
2. Discussion of Related Art
For decades, planar transistors have been fabricated on bulk semiconductor substrates. Transistor 100, as shown in FIG. 1A, is such a planar device. An active region, having opposite sidewalls 106 and 107, and a top surface 108, is formed between isolation regions 110 on bulk semiconductor substrate 101. The isolation regions 110 substantially cover the opposite sidewalls 106 and 107. The top semiconductor surface 108 is apportioned into, a source region 116, a drain region 117, and a channel region covered by a gate insulator 112 and a gate electrode 113. In the planar transistor design, the device is typically controlled or gated via the capacitive coupling between the top semiconductor surface 108 and the gate electrode 113. Because the channel is gated by a single gate electrode-semiconductor interface, the planar transistor is frequently called a single-gate device.
More recently, non-planar transistors have been under development to address the short channel effect (SCE) afflicting planar nano-scale transistors. A non-planar transistor is a transistor where the semiconductor channel is non-planar and the gate electrode couples to the channel through more than one surface plane, typically through sidewall portions formed by the non-planarity. Transistor 150, as shown in FIG. 1B, is such a non-planar device. An active semiconductor region, having opposite sidewalls 106 and 107, and a top surface 108, is formed over a substrate comprised of an isolation region 103 on a carrier 102. The top surface 108 and the opposite sidewalls 106 and 107 are apportioned into a source region 116, and a drain region 117, and a channel region covered by a gate insulator 112 and a gate electrode 113. In this transistor design, the device can be gated by the opposite sidewalls 106 and 107, as well as the top surface 108 of the device, reducing the SCE. Because the channel is gated by multiple gate electrode-semiconductor interfaces, the non-planar transistor is frequently called a multi-gate device.
Non-planar, or multi-gate, devices have been typically been formed upon substrates comprising an insulating layer, commonly called semiconductor-on-insulator (SOI). While there are many advantages to non-planar devices formed on SOI, there are also many disadvantages. For example, the channel width of a non-planar transistor on SOI is limited by the final thickness of the active silicon layer formed on the insulator layer of the SOI substrate. Thus, circuit designers are limited to a fundamental width and multiples of that width for all transistors of a circuit formed on the substrate. As shown in FIG. 1C, multiple non-planar bodies, each having a source 116 and drain 117 region are coupled by a common gate electrode 113 through a gate insulator 112 in an electrically parallel fashion to form device 175. Device 175 limits circuit design flexibility because the current carrying width must be incremented discretely, not continuously. Also, because of lithographic pitch limitations, non-planar transistors like device 175 shown in FIG. 1C incur a layout penalty relative to traditional planar transistors. Another disadvantage of devices formed on SOI is the commonly known “floating body” effect due to the buried insulator layer, which results in the loss of a ground plane for the transistors. Furthermore, non-planar transistors formed on SOI substrates suffer from poorer thermal conductivity and a higher overall cost than devices formed on bulk substrates.